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11. Senior Digital IC Design Engineer (Beijing)
Type: Full-time
Location: Beijing
Experience: 1-3 years
Degree: Bachelor’s or above
Language: N/A
Job Description
Responsibilities:
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Architecture definition according to product specifications.
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Logic design & implementation by Verilog on module level.
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Testbench generation, module/chip (or system) level verifications using Verilog, Vera, TCL or other verification languages.
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Design synthesis, DFT and timing analysis.
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Participate in test pattern generation, backend verification and layout review.
Qualifications and Requirements:
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Bachelor’s degree or above in Electronics, Telecommunications, Microelectronics Engineering or Computer Science.
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3+ years of work experience.
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2+ years of experience in digital design based on high-level languages (preferable Verilog), with knowledge of ASIC FE design flow, including coding, simulation, verification, synthesis, DFT and STA.
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Familiar with EDA tools from Synopsis, Cadence or Mentor, like NC-Verilog, VCS, DC/PC and PrimeTime.
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Familiar with digital video processing or DSP design is a plus.
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Good written and oral English communication skills.
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Good team player.
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